1. Field of the Invention
The present invention relates generally to an ultra-wideband (“UWB”) communication system, and, in particular, to an improved dual-mode frequency comparator and early-late detector for use in a UWB communication system.
2. Description of the Related Art
In general, in the descriptions that follow, we will italicize the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems. In addition, when we first introduce a term that we believe to be new or that we will use in a context that we believe to be new, we will bold the term and provide the definition that we intend to apply to that term. In addition, throughout this description, we will sometimes use the terms assert and negate when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, we may refer to the mutually exclusive boolean states as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, when we refer to a facility we mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless we expressly state to the contrary, we consider the form of instantiation of any facility that practices our invention as being purely a matter of design choice.
Shown in FIG. 1 is a UWB transceiver substantially as presented in FIG. 27a, “PHY signal flow”, on page 63 of the IEEE 802.15.4a-2007, the entirety of which is hereby expressly incorporated herein by reference (hereinafter “Standard”). In general, the construction and operation of the transceiver are disclosed in the Related Application 1. Shown in FIG. 2 is one embodiment of a UWB receiver adapted for use in the transceiver. In general, the construction and operation of the receiver are disclosed in the Related Application 2.
In general, UWB receivers incorporate circuits for detecting the frequency difference between a received signal and an internally generated reference signal. In addition, such receivers typically incorporate separate circuits for detecting the relative times of arrival of the leading/trailing edges of pulses of such pairs of signals. The following prior art embodiments of such circuits are known to us:    1. European Patent No. EP1916768A1, issued 30 Apr. 2008;    2. European Patent No. EP1916769B1, issued 13 Jan. 2010;    3. U.S. Pat. No. 7,719,373, issued 18 Apr. 2010;    4. US Patent Publication No. 2007/0257709, published 8 Nov. 2007;    5. U.S. Pat. No. 5,477,177, issued 19 Dec. 1995; and    6. J. Ryckaert, et al., “A 0.65-to-1.4 nJ per Burst 3-to-10 GHz UWB All-Digital TX in 90 nm for IEEE 802.15.4a”, IEEE ISSCC Dig. Tech. Papers, February 2007, pp. 120-121.
We submit that what is needed is a single circuit able to operate both as a frequency comparator and as an early-late detector without changes in its topology. In particular, when operating as a frequency comparator the state of the digital output of the circuit should indicate which of the two periodical signals applied at its inputs has a larger period/frequency; when operating as an early-late detector the state of the digital output of the circuit should indicate which of the two signals applied at its inputs presented first a rising or a falling edge. Further, we submit that a need exists for a calibration circuit for this dual-function circuit which significantly reduces the impact several non-idealities inherent to the physical implementation of the dual-function circuit may have on its operation. As a result, after calibration, the response of the dual-function circuit will not depend on circuit component (e.g., capacitors, switches) mismatches or on the offset voltage associated with a differential-input amplifier or comparator.